Distributed Queue Multi-Bus Architecture for Multi-CPU Chips

US 12,450,182, assigned to Faisal A. Qureshi, covers distributed queue multi-bus architecture for multi-cpu chips, and is available for sale or license through IPApproach.

US Patents

1 granted

Foreign Counterparts

2

Assignee

Faisal A. Qureshi

Availability

For Sale or License

Patents Included

• US 12,450,182↗

• CN 202380091242
• CN 120513448 A

Technology Highlights

• Deterministic Data Delivery Because data transmission begins only when a reservation reaches the front of its queue, transfer timing becomes predictable — critical for real-time and safety-critical multi-core workloads.
• Distributed Queue Management Reservation requests are added to a distributed queue located at the bus between source and destination nodes, enabling decentralized arbitration without a single bottleneck controller.
• Scalable Multi-CPU and GPU Architecture The reservation-queue method scales across any number of CPU and GPU nodes and bus segments, applying equally to dual-core embedded MCUs and many-core data center processors or chiplet arrays.
• Defined Path Determination A defined data routing process determines the optimal path between source and destination nodes for each reservation, supporting flexible multi-bus topologies across the chip.
• Foundational Interconnect IP As multi-core, multi-die, and chiplet designs proliferate, this patent provides foundational arbitration IP applicable to NoC fabrics, die-to-die interconnects, and emerging AI accelerator architectures.
• DISCLAIMER: THIS DOCUMENT PRESENTS AN OFFER FOR SALE OR LICENSING OF MENTIONED PATENTS/APPLICATION AND IN NO WAY PRESENTS A CASE OF INFRINGEMENT. ALL INFORMATION MENTIONED HEREIN IS FOR REPRESENTATION PURPOSE ONLY.

Listing updated August 27, 2026

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